The TCB-V24 provides bidirectional buffering in back-to-back RS-232 modem cross-connection applications such as a Tail Circuit. The 64-bit circular buffers compensate for differences between modem clock rates and limits errors to occasional data losses when the buffer overruns.
The RDS-TCB Tail-Circuit Buffer is designed to provide
selectable bi-directional buffering between two data circuits
that are operating at nominally the same clock rate and are capable
of providing clocking as a DCE. In such cases, the timing of the
two circuits is not locked to the same timing source, or may be
allowed to deviate from a common timing source for a length of
time. The RDS-TCB meets this need by providing selectable amounts
of bi-directional memory from 1,024 bits up to 8,192 bits and
supports synchronous clock rates up to 2.048 Mbps.
The RDS-SB is a device intended to provide a unidirectional
2.097 Mbit elastic data buffering (FIFO memory) function between two systems
having nominally equivalent clocking rates. The two systems may be either
running asynchronously, or may be traceable to a common timing source.
The Selectable Transmit Buffer (RSD-STB) allows DCE to DTE
connections at data rates up to 10Mbps.
Allows the user to even the network delays between a terrestrial and
satellite network for transactions.